A Low Latency Arbitration Circuit

Indexing terms: Asynchronous circuits, Arbiters We present an asynchronous circuit for an arbiter cell that can be used to construct cascaded multi-way arbitration circuits. The circuit is completely speed-independent. It has a short response delay at the input request-grant handshake link due to both (a) the propagation of requests in parallel with starting arbitration, and (b) the concurrent resetting of request-grant handshakes in diierent cascades of a request-grant propagation chain. Arbitration circuits are commonplace in digital systems with a single resource allocated to diier-ent user processes. The typical examples are systems with shared busses, multi-port memories, packet routers to name but a few. An asynchronous arbiter is deened as a circuit that dynamically allocates a single shared resource to the user components in a system which is free from common clock. Each user, when requires the resource, issues an asynchronous request and waits until the arbiter produces a grant. The user then uses the resource and after nishing its action releases its request. This results in a subsequent release of the grant, after which the user can issue another request and so on. The arbiter, when it receives a number of active requests from diierent users, generates after some nite delay a grant to exactly one of them and leaves other requests pending until the granted user has released the request. The arbiter then releases the grant and, if there are pending requests, produces another active grant, again on a mutually exclusive basis. We consider a standard basic cell of a multi-way arbiter that arbitrates between two users. Multi-way arbitration is organised by building a cascade of such cells to form a tree or a linear structure. Each cell thus propagates the request in the direction from the lower level to the higher level of the structure, while the grants are generated in the opposite direction. Figure 1.(a) shows one such cell, a 2-way arbiter, with its three request-grant handshake links (R1,G1), (R2,G2) and (R,G), where (R1,G1) and (R2,G2) stand for the links with lower level cascades, generating competing requests at R1 and R2, and the (R,G) pair is the link with the higher level cascade. An example of a 4-way arbiter, shown in Figure 1.(b), illustrates the regular way in which a cascaded multi-way arbiter can be composed from the basic cells. Figure 1.(c) illustrates the handshaking protocol between the links. After a rst request by R1 is granted …